# VLSI Design; 4-bit Up/Down Counter with Parallel Input

Last semester, I took a VLSI class. The class included a project and a written examination. The project was on VLSI Design (duh?) and, to be specific, we had to implement a 4-bit Up/Down Counter with Parallel Input from scratch. Yes, that means we designed our own gates from discrete transistors and built our final circuit one block at a time.

First of all, let us discuss a little bit about transistors. There are many kinds of transistors but, in general, they all fall under two main categories, Bipolar Junction Transistors (BJT) and Field Effect Transistors (FET). All transistors control one value using an other value (and by “value”, I mean current or voltage). Their main difference is how they do it. There are tons of sites, videos and books out there where you can learn about the workings of a transistor, so we will focus on the Enhancement Metal-Oxide Semiconductor FET because it is our workhorse.

In general, these devices either conduct current from source (S) to drain (D) for the p-channel transistor and from drain (D) to source (S) for the n-channel transistor or they don’t. The conduction depends on the gate (G) to source (S) voltage (VGS). The transistors are active (or ON, as we usually say) when |VGS|>|Vth|, where Vth is the threshold voltage of the transistor and we can assume it is a constant. The fourth pin is called the body (B) and is related to the body effect. It is not a concern for us and we will just connect it to the most positive (PMOS) or the most negative (NMOS) power supply.

Now that we learned a few things about transistors, let’s use them to design our first logic circuit, the NAND gate. We have designed and emulated everything through Cadence. A NAND gate implements the logic function AND followed by the logic function NOT. Perhaps, this choice comes as a surprise. Why not AND or NOT? The answer is simple. We can construct both AND and NOT using the NAND gate. Actually, we can construct any digital circuit having in our arsenal only NAND gates!

As you can see, it is a very simple implementation. You can see some additional parameters in the transistors. These are the width and length of the conduction channel. Bigger channel means more current can pass and we usually make PMOS transistors with bigger channels than NMOS transistors, because NMOS conducts better. If you are familiar with the basics of logic design, you know how we can build a NOT or an AND gate using what we have so far. For the rest of you, think about it for a minute before you move to the next paragraph.

Well, the NOT gate is obvious. Just short-circuit the NAND inputs. Now the AND gate is obvious, as well. Just connect NOT to the NAND output. I will not show every circuit in the main post, as I don’t want to ruin its layout. However, I will publish them under a spoiler tag.

Full Circuit Collection

Now that we have built every basic logic gate (NAND, NOT, NOR, 3 input NAND, AND, OR, XOR) we are going to implement some more advanced logic functions. Can you find out what the next circuit does?

I hope the top schematic didn’t give away the answer, because it is the well know symbol for the Multiplexer. The output Y is equal to I0, if S=0, and I1, if S=1. Now, if you can find what the next circuit does without looking further, you are really good!

Yeah! It’s a D Flip-flop! Here’s the full picture.

A Flip-flop stores one bit of information (0 or 1). The positive-edge-triggered D Flip-flop stores the logic value of its D input, when the CLK goes from 0 to 1. The Q pin is equal to its stored bit and the Q’ pin is the inverse of Q. R stands for Reset and sets the Flip-Flop to its original state.

Our final circuit, before we move on to the 4-bit counter, is the T Flip-flop. A positive-edge-triggered T Flip-flop stores one bit of information, just like the D Flip-Flop, but they operate differently. When the CLK goes from 0 to 1, the D Flip-Flop stores the value of tis D input. On the other hand, the T Flip-flop inverses its stored value if its T input is 1 and maintains its stored value if T=0. That may seem like a weird property for a Flip-flop but it is of high importance for our final design. We will use T Flip-flops to our final implementation and the only reason why we constructed D Flip-flops is to use them in order to make T Flip-flops.

OK, are you ready? Here it is!

Got pretty big, didn’t it? Its real world representation is even more scary because it contains 404 transistors. When I started building it, I underestimated the number of transistors I am going to need. I remind you that everything you see in this picture is made by the circuits we saw earlier in this post. And this is just a 4 bit counter. Now I realize why CPUs have billions of transistors and how important their miniaturization is.

But enough with the talk, let’s analyze. Why is this a 4-bit Up/Down Counter with Parallel Input? For the analysis, we omit the signals ENABLE, CLOCK and reset. Their function is obvious. Notice that the pin Count/Load defines our operation mode. For Count/Load=0 we have an Up/Down Counter and the circuit is getting simplified to this.

Notice that whether Up/Down is 0 or 1, the T input of the first flip flop is always 1. This is necessary because when you count the Least Significant Bit is always changing. If Up/Down=0, then the second column of AND gates is getting nullified. So, the input T of a flip flop is getting 1 only if all the previous inverse outputs are 1. For example, if A0=0 and A1=0, then A0’=1 and A1’=1. That means T2=1 and in the next clock period A2=A2′. That means Up/Down=0 starts a Down count. Of course, Up/Down=1 starts an Up count. In addition, if every flip flop is in 0 (1) state and the Up/Down pin is 0 (1), the counter resets itself to 1111 (0000).

When Count/Load=1, we get the circuit below.

I don’t think there is much to explain. A T Flip-flop connected with a XOR gate like that is a D Flip-flop. Remember that the output of a XOR gate is 0 if its inputs are equal and 1 otherwise. So, if the output of the T Flip-flop is the same with the input of the XOR gate, then the XOR gate will keep its T input low and the next clock will not change its content. But if the value stored in the T Flip-flop is different than the one we want to store in it, the XOR gate will set high the T input and the next clock will inverse its content. This is how the parallel input mechanism works.